The present invention relates to a semiconductor memory device, and more precisely to a data output control circuit for controlling a data output in a read operation and a data output control method.
In general, a semiconductor memory device controls the output timing of data read through a data output control circuit so as to transmit data from a memory cell after a read instruction to the outside in a corresponding clock cycle for each CAS latency CL.
Such a conventional data output control circuit may be configured as shown in FIG. 1. Its operation is described below with reference to FIG. 2, which illustrates waveforms of the data output control circuit of FIG. 1 in a case where a CAS latency is 5 (CL=5).
First, a read command signal READ generated in a read operation is output as an internal read command signal RDCMD from the read command generator 1 after ‘tCMD’ seconds and after an external clock CLK is output as a DLL clock DLLCLK having a negative delay through a delay locked loop 2.
The term ‘tCMD’ denotes a time that is delayed until an internal read command signal RDCMD is generated from a rising edge of an external clock CLK to which a read command signal READ is applied. Further, the DLL clock signal DLLCLK is a signal used to synchronize data DATA, to an external clock signal CLK when the data DATA is output as DQ by compensating for an output delay time within a memory.
Thereafter, the internal read command signal RDCMD is shifted four times through a count shifter 3 in accordance with the CAS latency CL to be output as a data output control signal OUTEN. Further, the data DATA is delayed by ‘tDO+a’ in the data output control signal OUTEN and synchronized to a rising edge of the external clock signal CLK to be output as the DQ.
The count shifter 3 shifts or delays the internal read command signal RDCMD by ‘tOED,’ in which ‘tCMD,’ ‘tDO’ and ‘a’ are subtracted from a CAS latency count delay time, the ‘tCMD’ being a time delayed until an internal read command signal RDCMD is generated from a CAS latency count delay time after a read instruction, the ‘tDO’ denoting a time difference between an external clock signal CLK and a DLL clock signal DLLCLK, and the ‘a’ being a time for securing a data margin. At this time, each of the generated clock signals OUT_PRE1 to OUT_PRE3 has a certain shifting margin due to the DLL clock DLLCLK.
Since the cycle of an external clock signal CLK is reduced as frequencies become high, the time at which read data DATA is output as DQ becomes shortened by the reduced cycle. On the contrary, since ‘tCMD’ and ‘tDO’ are not changed, ‘tOED’ is reduced.
If ‘tOED’ is reduced, the shifting margin of each clock signal OUT_PRE1 to OUT_PRE3 becomes small. Further, if such a shifting margin reaches a limit, the phase and pulse width of each clock signal OUT_PRE1 to OUT_PRE3 or an output enable signal OUTEN may be distorted during a shifting operation.
As an example, in a case where the count shifter 3 includes a plurality of flip flops (not shown), each of the flip flops shifts a clock signal input from an rising edge of a DLL clock signal DLLCLK. At this time, if the pulse width of the DLL clock signal DLLCLK is reduced due to a high-frequency operation, there may occur a case where each of the flip flops does not shift a clock signal at an exact time point.
If the phase and pulse width of each clock signal OUT_PRE1 to OUT_PRE3 or an output enable signal OUTEN is distorted due to such a case, read data is not output at an exact time point. As a result, there is a problem in that a failure may occur.